The present disclosure relates to a signal line connection structure and apparatuses using the same.
The liquid crystal display (LCD) as an important flat display mode has been developing fast for more than ten years. The liquid crystal display carries the advantages of light weight, thinness and low power consumption, etc, and is broadly applied in modern information apparatuses such as televisions, computers, cell-phones, digital cameras and so on.
A liquid crystal (LC) panel generally comprises an array substrate, a color film substrate and a LC layer between the two substrates. The array substrate comprises a thin film transistor (TFT) circuit in the pixel area and a peripheral circuit in the peripheral area. The color film comprises red, green, and blue (RGB) resins and a black matrix. The displaying is realized through controlling the throughput of the light by controlling the ON-OFF of the TFTs to control the twist of the LC. The ON-OFF of the TFTs is controlled by signals. Typically, the controlling is obtained by introducing the signals into the TFTs in the pixel area through signal lines in the peripheral circuit.
As shown in FIG. 1A, in the schematic diagram for the connection of the signal lines in the peripheral circuit of an LCD device in prior art, a first signal line 11a and a second signal line 21a are overlapped partially, and a respective insulating protection layer exists in their middle and the outermost layers to insulate the signal lines from each other. Though holes 12a and 22a are created respectively in insulating layers of the first signal line 11a and the second signal line 21a, and then an Indium Tin Oxide (ITO) layer 4a is plated on the though holes. The first signal line 11a and the second signal line 21a are connected though the ITO layer 4a on the though holes 12a and 22a in order to conduct signals.
FIG. 1B is the cross section in the AA′ direction in FIG. 1A, the array substrate comprises a glass substrate 1, protection layers 3 and 5. During the production process of the array substrate, static charges are easy to concentrate at the though holes 12a and 22a after the through holes are created in the insulating layers of the first signal line 11a and the second signal line 21a. When the ITO layer 4a is plated on the through holes, the static charges concentrated at the through hole 12a of the first signal line 11a and the through 22a of the second signal line 21a will be discharged through the ITO layer 4a, which would generate a large current to burn down the ITO layer 4a. As a result, the signal transmission in the first signal line 11a and the second signal line 21a is broken.
Two ways exit currently to prevent the circuit from being damaged by discharging of the static charges. The first way is to increase the resistance of the first signal line 11a and the second signal line 21a, such that the ITO layer 4a is protected though the method in which the discharging current is reduced by decreasing the voltage of the ITO layer 4a at the through holes. The other way as shown in FIG. 2 is to increase the area of the through holes, such that the partial voltage of the ITO layer 4a at the through holes is reduced by decreasing the contact resistance of the first signal line 11a and the second signal line 21a. 
The above-mentioned two ways are able to protect the ITO layer by reducing the discharging of the static charges to some extent; however, if the static voltage is relatively high, the discharging of the static charges still occurs from time to time, and the ITO layer covered on the through holes is burned down, which makes the signal transmission of the first signal line and the second signal line broken.